Recently, a hand-held image display system and a portable multimedia image display system mostly have smaller and lower resolution display element because of minimization and convenience. According to a signal resource such as signal of a television and a display card, the resolution of the signal resource has been defined in the past and is larger than the necessary resolution of the above-mentioned product (i.e., the above-mentioned image display system), and therefore it is more important to have a image processing circuit with the selective reduction of image and low power consumption.
A conventional method for image reducing processing circuit utilizes the architecture of a line buffer in order to get more completely image data in the subsequent process. An inputted image data is temporarily stored in a memory line by line and then is processed. Because the architecture of the line buffer is utilized, a memory implements the reading and writing and can processes input image data and output image data with different frequency at the same time so as to increase the complexity of circuit. Furthermore, the memory stores the data of whole line, and therefore the requirement for the capacity of the memory is increased as well.
Referring to FIGS. 1 and 2, the architecture of the image reducing processing circuit includes a pre-position data processing unit 10, a line buffer units 11, a vertical direction image processing unit 12, a horizontal direction image processing unit 13 and a post-position data processing unit 14. The image data (i.e., original images 1a) are firstly processed by the pre-position data processing unit 10, and then the original image 1a with the same first access frequency 1c is delivered to the line buffer units 11. According to the input sequence of the image data, the image data is stored to N sets of the line buffer 120, the vertical direction image processing unit 12, and the horizontal direction image processing unit 13 one by one. With the second frequency 1d, the image data is processed in parallel way by the line buffer unit 11 and finally delivered to the post-position processing unit 14 so as to output a reduced image 1b. 
In conclusion, the size of the reduced image 1b is smaller than that of the input original image 1a in the above-mentioned architecture of the image reducing processing circuit. Because of using the architecture of the line buffer unit 11, the memory depth of the line buffer unit 11 will be designed and the same as that of the original image 1a. If the size of the input original image 1a is much bigger than that of the output reduced image 1b, the capacity of the memory will be increased. The first frequency 1c and the second frequency 1d are used in the input and output of the line buffer unit 11 at the same time and are access frequency both, and therefore the circuit complexity of the memory during the memory implement the readout and writing of the image data at the same time.
Accordingly, there exists a need for the method for the image reducing processing circuit to solve the above-mentioned problems and disadvantages.